Field
Embodiments of the present disclosure generally relate to methods for patterning a semiconductor substrate. More particularly, embodiments of the present disclosure relate to method of forming a pattern with rectangular openings.
Description of the Related Art
The continued demand for miniaturization in circuit technology has driven the size of circuit features to below 10 nm. Patterning features in such scale becomes extremely challenging. Double patterning and quadruple patterning have been adopted to achieve in patterning line gratings. However, the state-of-art double patterning and quadruple patterning technology cannot achieve the same level of success in patterning “cuts”, i.e. rectangular features. Overlay errors due to multiple exposures required to patterning cuts, edge placement errors, and etch proximity effects, among other errors, become more pronounced in patterning cuts.
Therefore, there is a need for improved patterning schemes for forming rectangular features.